Prof. Lai Wang, Tsinghua University, China
Bio: Lai Wang is a tenured professor in the Department of Electronic Engineering at Tsinghua University, Deputy Director of the Office of Human Resources and Deputy Director of the Talent Office at Tsinghua University, and a recipient of the National Science Fund for Distinguished Young Scholars. He received his bachelor’s and doctoral degrees from the Department of Electronic Engineering at Tsinghua University in 2003 and 2008, respectively. He has long been engaged in research on wide-bandgap semiconductor optoelectronic materials and devices; his research interests in recent years include GaN-based micro-LEDs, blue-green lasers, and integrated sensing, storage, and computing chips. He has led nine research projects, including those under the National Key Research and Development Program and the National Natural Science Foundation of China. He has published over 100 SCI-indexed papers. He serves on the editorial board of *Applied Physics Express* and as a young editorial board member for *Journal of Semiconductors*, *Journal of Luminescence*, and *Journal of Artificial Crystals*. In 2011, he was awarded the Second Prize of the National Science and Technology Progress Award.
Prof. Yue Zhang, Beihang University, China
Bio: Yue Zhang is currently full professor and executive vice dean of School of Integrated Circuit Science and Engineering, Beihang University, China. His current research focuses on spintronics, emerging non-volatile memory technologies and hybrid low-power circuit designs. He has authored more than 150 scientific papers, including Nature Materials、Nature Electronics、Nature Communications、Science Advances、IEDM, etc. He is the recipient of the National Science Fund for Excellent Young Scholars, the Young Elite Scientist Sponsorship Program of CAST. He is serving IEEE transactions on Circuits and Systems-I: Regular Papers as associate editor and served as general chair of NANOARCH’19.
Speech Title: Spintronic Integrated Circuits for Post-Moore Era
Abstract: Spintronics technology realizes non-volatile data storage by leveraging the intrinsic spin property of electrons. Featuring outstanding advantages including low power consumption, high speed, ultra-high storage density and radiation resistance, it is expected to break through the power consumption bottleneck of conventional CMOS processes and underpin the rapid advancement of emerging applications such as the Internet of Things (IoT) and artificial intelligence (AI). Magnetoresistive Random Access Memory (MRAM), a type of spintronic memory, stands as a representative technical solution for novel ultra-low-power memory devices and has been successfully deployed in aerospace and wearable electronics. By integrating non-volatile storage with reconfigurable logic computing functions, MRAM can be further assembled to construct a processing-in-memory architecture, offering an effective solution to the bottleneck of the von Neumann architecture. This speech presents the latest research progress and prospects of spintronic integrated circuits from multiple dimensions, including functional material deposition, fundamental physical mechanism investigation, device structure optimization, and chip development.
Prof. Weifeng Lü,Hangzhou Dianzi University, China
Bio: Weifeng Lü is now a Professor at the School of Electronic and Information (School of Integrated Circuit Science and Engineering), Hangzhou Dianzi University. He is a member of both the Chinese Institute of Electronics and the China Computer Federation. He received his Bachelor's and Master's degrees from the Department of Information Science and Electronic Engineering, and his Ph.D. from the School of Electrical Engineering, all at Zhejiang University. He was also a visiting scholar at the University of Texas at Austin, USA. His research primarily focuses on ultra-low-power hafnium-based ferroelectric negative-capacitance logic devices, ferroelectric field-effect-transistor (FeFET) memories, computing-in-memory circuits, as well as the awareness and statistical analysis of process variations in these devices and circuits. He has served as Principal Investigator for multiple projects funded by the National Natural Science Foundation of China and the Natural Science Foundation of Zhejiang Province. He has also been invited to serve as a reviewer for over 30 SCI-indexed journals in his field internationally.
Speech Title: Modeling and Estimation of Crystal Phase Variation Effects on Hafnium-Based Ferroelectric Devices
Abstract: Hafnium-based ferroelectric materials, such as hafnium zirconium oxide (HZO), have enabled devices including negative-capacitance field-effect transistors (NCFETs) and ferroelectric field-effect transistors (FeFETs), which demonstrate substantial promise for ultralow-power logic, memory, and computing in-memory applications. However, crystal phase variation within the ferroelectric layer introduces performance degradation and yield loss. Robust modeling and estimation of the impact of such variation are essential to shorten chip development cycles and reduce associated costs. In this talk, we develop a mixed-phase distribution model of the ferroelectric layer through a nucleation-based modeling approach of grain formation, which enables a systematic investigation into the effects of ferroelectric/ dielectric phase probability, geometric morphology, and spatial distribution on the electrical performance of HZO-based NCFETs and FeFETs. By employing Monte Carlo sampling to generate a large number of statistical instances, we extract the statistical characteristics of device performance parameters, thereby facilitating the fitting of statistical distributions and the analytical derivation of probability density functions for these parameters. This study provides a theoretical and methodological foundation for performance optimization and early-stage prediction in the manufacturing of practical hafnium-based ferroelectric devices and circuits.
Prof. Zhiting Lin, Anhui University, China
Bio: Zhiting Lin, a professor at the School of Integrated Circuits at Anhui University and a Senior Member of the IEEE, has long been engaged in research on analog integrated circuit design, focusing on the speed, power consumption, and area bottlenecks of memory chips. He has collaborated closely with leading companies in the industry to help ensure China’s self-reliance and control over core technologies. He has received support from initiatives such as the Central WXB Talent Program and the National Youth Talent Program. He has led multiple research projects, including a sub-project under the National Key R&D Program and general grants from the National Natural Science Foundation of China. He has published over 100 papers in top-tier journals and conferences such as JSSC and ISSCC, holds more than 170 authorized patents, and has been listed among the top 2% of scientists worldwide. He has received honors including the Anhui Provincial Special Prize for Teaching Achievements, the Baosteel Outstanding Teacher Award, and the title of Outstanding Graduate Advisor in Anhui Province.
Speech Title: An Energy-Efficient SRAM Computing-in-Memory Chip with Reconfigurable Dataflow for Edge AI Inference
Abstract: To break the "Memory Wall" bottleneck where data movement consumes over 60% of total system energy during edge inference, this research presents an energy-efficient SRAM Computing-in-Memory (CIM) chip design. The architecture implements a mixed-granularity computing framework where 64 computational units are embedded directly into the SRAM array, enabling inputs, weights, and outputs to flow locally within the chip and thoroughly eliminating off-chip data-transportation overhead. To address interconnection complexity and strict silicon area constraints, the chip utilizes a hierarchical on-chip dataflow network that balances hardware footprint with high-efficiency data routing and reuse through a grouped-bus topology instead of conventional all-to-all interconnects. Furthermore, a dynamically reconfigurable Full Adder (FA) array is implemented via time-multiplexing and dynamic mode-switching to replace traditional fixed multipliers and independent adder trees, drastically shrinking the core footprint while guaranteeing 20-bit full-precision accumulation and seamlessly integrating low-overhead multi-mode pooling units directly into the data pathway. By successfully mitigating data-transportation bottlenecks and hardware area constraints, this scalable SRAM-CIM design achieves a harmony of high precision, ultra-low power consumption, and versatile algorithmic adaptability, delivering a highly efficient hardware foundation for next-generation intelligent edge devices.
Assoc. Prof. Liang Qi, Shanghai Jiao Tong University, China
Bio: Liang Qi is an associate professor and doctoral advisor at Shanghai Jiao Tong University and has been selected as a Young Yangtze River Scholar by the Ministry of Education. For the past decade, he has focused on the design and systems of analog and mixed-signal integrated circuits. He previously served as a senior engineer in the Wireless RF Department at Huawei HiSilicon, where he led the design of multi-mode (2G–5G) RX ADCs, which have since entered mass production. Over the past five years, he has led government-funded projects such as the National Key R&D Program’s “Strategic Science and Technology Innovation Cooperation” key project, General and Young Investigator grants from the National Natural Science Foundation of China, and the Shanghai Municipal International Science and Technology Cooperation Project; he has also led industry-sponsored projects for leading companies such as Huawei HiSilicon and Goertek. Over the past five years, he has published more than 38 peer-reviewed papers as first or corresponding author, including in top conferences and journals in the field of integrated circuit design, such as ISSCC, CICC, ASSCC, JSSC, and TCAS-I. He received the IEEE ASICON Outstanding Young Scholar Paper Award (first author, 2021) and was named a “Outstanding New Employee” by Huawei HiSilicon (2020). In terms of academic service, the applicant currently serves on the editorial boards of IEEE Trans. CAS-I (Q1) and IEEE Trans. CAS-II (Q1), as well as the domestic high-impact journal ICAS; is a young editorial board member of the Chinese Core Journal *Microelectronics*; and is a member of the Technical Committee for the IEEE ESSERC conference (the flagship conference on solid-state circuits in Europe).
Speech Title: Chips Connecting to the Brain: Technological Divergence and Convergence Trends in Non-Invasive and Invasive Brain-Computer Interfaces
Abstract: Brain-computer interfaces (BCIs) are transitioning from laboratory exploration toward broader application scenarios including clinical rehabilitation, intelligent interaction, and neural enhancement—with chips serving as the core determinant of system capability boundaries. Non-invasive BCIs prioritize high-sensitivity acquisition of weak neural signals, low-noise amplification, portable low-power operation, and edge-side intelligent processing. Invasive BCIs, in contrast, place greater emphasis on high-channel-density recording, long-term stability, biocompatibility, wireless data transmission, and closed-loop stimulation capabilities. This talk compares the divergent requirements imposed by non-invasive and invasive pathways on chip architecture and performance metrics, reviews the current state of technology and industrial development both domestically and internationally, and forecasts future evolutionary trends in BCI chips toward higher integration, flexible form factors, ultra-low power consumption, on-chip intelligence, and the convergence of sensing, computation, and stimulation functionalities.